BelaSigna 200
6.1.2. Instruction Set
The RCore instruction set can be divided into the following three classes:
1. Arithmetic and Logic Instructions
The RCore uses two's complement fractional as a native data format. Thus, the range of valid numbers is [-1; 1), which is represented
by 0x8000 to 0x7FFF. Other formats can be utilized by applying appropriate shifts to the data.
The multiplier takes 16-bit values and performs a multiplication every time an operand is loaded into either the X or Y register. A
number of instructions that allow loading of X and Y simultaneously and addition of the new product to the previous product (a MAC
operation), are available. Single-cycle MAC with data pointer update and fetch is supported.
The arithmetic logic unit (ALU) receives its input from either the accumpulator (AE|AH|AL) or the product register (PH|PL). Although the
RCORE is a 16-bit system, 32-bit additions or subtractions are also supported. Bit manipulation is also available on the accumulator as
well as operations to perform arithmetic or logic shifts, toggling of specific bits, limiting, and other functions.
2. Data Movement Instructions
Data movement instructions transfer data between RAM, control registers and the RCore’s internal registers (accumulator, PH, PL, etc).
Two address generators are available to simultaneously generate two addresses in a single cycle. The address pointers R0..2 and
R4..6 can be configured to support increment, decrement, add-by-offset, and two types of modulo-N circular buffer operations. Single-
cycle access to low X memory or low Y memory as well as two-cycle instructions for immediate access to any address are also
available.
3. Program Flow Control Instructions
The RCore supports repeating of both single-word instructions and larger segments of code using dedicated repeat instructions or
hardware loop counters. Furthermore, instructions to manipulate the program counter (PC) register such as calls to subroutines,
conditional branches and unconditional branches are also provided.
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