BelaSigna 200
7.0 Instruction Set
Table 6: Instruction Set
Instruction
Description
Instruction
Description
ABS A [,Cond] [,DW]
ADD A, Reg [,C]
ADD A, (Rij) [,C]
ADD A, DRAM [,B]
Calculate absolute value of A on condition
Add register to A
DCMP
Compare PH | PL to A
DEC A [,Cond] [,DW]
DEC Reg [Cond]
DEC (Rij) [,Cond]
Decrement A on condition
Decrement register on condition
Decrement memory on condition
Add memory to A
Add (DRAM) to A
Subtract PH | PL from A,
update PH | PL on condition
ADD A, (Rij)p [,C]
Add program memory to A
DSUB [Cond] [,P]
ADD A, Rc [,C]
ADDI A, IMM [,C]
ADSI A, SIMM
Add Rc register to A
Add IMM to A
EOR A, Reg
Exclusive-OR register with AH to AH
Exclusive-OR memory with AH to AH
Exclusive-OR (DRAM) with AH to AH
EOR A, (Rij)
Add signed SIMM to A
EOR A, DRAM [,B]
Exclusive-OR program memory with
AH to AH
AND A, Reg
AND register with AH to AH
EOR A, (Rij)p
Exclusive-OR Rc register with AH to
AH
AND A, (Rij)
AND memory with AH to AH
EOR A, Rc
AND A, DRAM [,B]
AND A, (Rij)p
AND (DRAM) with AH to AH
EORI A, IMM
EOSI A, SIMM
Exclusive-OR IMM with AH to AH
Exclusive-OR unsigned SIMM with AH
to AH
AND program memory with AH to AH
AND A, Rc
AND Rc register with AH to AH
AND IMM with AH to AH
INC A [,Cond] [,DW]
INC Reg [,Cond]
INC (Rij) [,Cond]
LD Rc, Rc
Increment A on condition
ANDI A, IMM
ANSI A, SIMM
BRA PRAM [,Cond]
BREAK
Increment register on condition
Increment memory on condition
Load Rc register with Rc register
Load register with register
AND unsigned SIMM with AH to AH
Branch to new address on condition
Stop the DSP for debugging purposes
LD Reg, Reg
Push PC and branch to new address
on condition
CALL PRAM [,Cond] [,B]
LD Reg, (Rij)
Load register with memory
CLB A
Calculate the leading bits on A
Clear accumulator
LD (Rij), Reg
LD A, DRAM [,B]
LD DRAM, A [,B]
LD Rc, (Rij)
Load memory with register
Load A with (DRAM)
CLR A [,DW]
CLR Reg
Clear register
Load (DRAM) with A
CMP A, Reg [,C]
CMP A, (Rij) [,C]
CMP A, DRAM [,B]
CMP A, (Rij)p [,C]
Compare register to A
Compare memory to A
Compare (DRAM) to A
Compare program memory to A
Load Rc register with memory
Load memory with Rc register
Load register with program memory
Load program memory with register
LD (Rij), Rc
LD Reg, (Rij)p
LD (Rij)p, Reg
Load register with program memory via
register
CMP A, Rc [,C]
Compare Rc register to A
LD Reg, (Reg)p
CMPI A, IMM [,C]
CMSI A, SIMM
Compare IMM to A
LD Reg, Rc
LD Rc, Reg
LDI Reg, IMM
Load register with Rc register
Load Rc register with register
Load register with IMM
Compare signed SIMM to A
Calculate logical inverse of A on condition
CMPL A [,Cond] [,DW]
Add PH | PL to A, update PH | PL
on condition
DADD [Cond] [,P]
DBNZ0/1 PRAM
LDI Rc, IMM
Load Rc register with IMM
Load memory with IMM
Branch to new address if LC0/1 <> 0
LDI (Rij), IMM
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