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0W344-005-XTP 参数 Datasheet PDF下载

0W344-005-XTP图片预览
型号: 0W344-005-XTP
PDF下载: 下载PDF文件 查看货源
内容描述: 1.0 GENRAL说明 [1.0 Genral Description]
分类和应用:
文件页数/大小: 43 页 / 1433 K
品牌: ONSEMI [ ONSEMI ]
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BelaSigna 200  
4.2.2. CSP Pad Out  
Table 4: Pad Out (Advance Information)  
Pad  
Pad Name  
Index  
Pad Function  
I/O  
U/D  
B2  
A2  
A1  
C3  
B3  
B1  
C2  
C1  
B4  
C4  
D1  
E1  
D2  
D3  
E3  
D4  
E2  
E5  
A6  
E6  
D6  
E7  
D7  
E8  
D8  
C8  
C7  
B8  
C6  
A8  
B7  
A7  
B6  
A5  
B5  
CAP0  
Charge pump capacitor pin 0  
N/A  
N/A  
O
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
U
CAP1  
Charge pump capacitor pin 1  
VDBL  
Double voltage  
VREG  
Regulated voltage for microphone bias  
Audio signal input to ADC0  
O
A|0  
I
A|1/LOUT  
A|2  
Audio signal input to ADC0/line level output signal from preamp 0  
Audio signal input to ADC1  
I/O  
I
A|3  
Audio signal input to ADC1  
I
A|R  
Reference voltage for microphone  
Analog ground  
N/A  
N/A  
N/A  
O
AGND  
AOR  
Reference voltage for DAC  
AO1/RCVR1-  
AO0/RCVR1+  
RCVR0-  
Audio signal output from DAC1/output from direct digital drive 1-  
Audio signal output from DAC0/output from direct digital drive 1+  
Output from direct digital drive 0  
Output from direct digital drive 0  
Receiver return current  
O
O
RCVR0+  
O
RCVRGND  
VBAT  
N/A  
I
Positive power supply  
VDD  
Core logic, EEPROM and pad supply  
Digital pads ground  
I
GNDO  
N/A  
N/A  
I/O  
I
GNDC  
Core logic and pads ground  
EXT_CLK  
DEBUG_RX  
DEBUG_TX  
TWSS_SDA  
TWSS_CLK  
SPI_SERO  
SPI_SERI  
SPI_CS  
External clock input/internal clock output  
Debug port receive  
U
Debut port transmit  
O
U
TWSS data  
I/O  
I
U
TWSS clock  
U
Serial peripheral interface serial data out  
Serial peripheral interface serial data in  
Serial peripheral interface chip select  
Serial peripheral interface clock  
General-purpose I/O/PCM interface frame  
General-purpose I/O/PCM interface output  
General-purpose I/O/PCM interface input  
General-purpose I/O/PCM interface clock  
General-purpose I/O/class D receiver clock  
Low-speed A/D/general-purpose I/O/general-purpose UART receive  
I/O  
I
D
U
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
D
SPI_CLK  
N/A  
U
GPIO[14]/PCM_FRAME  
GPIO[13]/PCM_OUT  
GPIO[12]/PCM_IN  
GPIO[11]/PCM_CLK  
GPIO[10]/DCLK  
LSAD[5]/GPIO[9]/UART_RX  
U
U
U
U
U
Low-speed A/D input/general-purpose I/O/general-purpose UART  
transmit  
A4  
C5  
A3  
LSAD[4]/GPIO[8]/UART_TX  
LSAD[3]/GPIO[7]  
I/O  
I/O  
I/O  
U
U
U
Low-speed A/D input/general purpose I/P  
LSAD[1]/GPIO[5]/I2S_OUT  
A
Low-speed A/D inputs/general-purpose I/O/I2S interface analog  
blocks output  
LSAD[0]/GPIO[4]/I2S_OUT  
D
Low-speed A/D inputs/general-purpose I/O/I2S interface analog  
blocks output  
D5  
E4  
I/O  
I/O  
U
U
GPIO[3]/  
NCLK_DIV_RESET/I2S_FA  
General-purpose I/O/clock divider reset/I2S interface analog blocks  
frame output  
Rev. 16 | Page 12 of 43 | www.onsemi.com