PEDL9041A-02
OKI Semiconductor
ML9041A-xxA/xxB
Instruction Codes
Table of Instruction Codes
Execution
Time
f = 270 kHz
Code
Instruction
Function
RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clears all the displayed digits of the
LCD and sets the DDRAM address 0 in
the address counter. The arbitrator
data is cleared.
Display Clear
Cursor Home
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
S
1.52 ms
1.52 ms
37 µs
Sets the DDRAM address 0 in the
address counter and shifts the display
back to the original. The content of the
DDRAM remains unchanged.
Determines the direction of movement
of the cursor and whether or not to shift
the display. This instruction is
Entry Mode
Setting
0
1
1
I/D
executed when data is written or read.
Sets LCD display ON/OFF (D), cursor
ON/OFF or cursor-position character
blinking ON/OFF.
Display
ON/OFF Control
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
1
D
C
X
X
B
X
X
37 µs
37 µs
37 µs
37 µs
37 µs
0 µs
Moves the cursor or shifts the display
without changing the content of the
DDRAM.
Cursor/Display
Shift
S/C R/L
Sets the interface data length (DL), the
number of display lines (N) or the type
of character font (F).
Function Setting
0
DL
N
F
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.
CGRAM
Address Setting
0
ACG
Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.
DDRAM
Address Setting
1
ADD
ADC
Reads the Busy Flag (indicating that
the ML9041A is operating) and the
content of the address counter.
Busy Flag/
Address Read
BF
Writes data in DDRAM, ABRAM or
CGRAM.
RAM Data Write
RAM Data Read
1
1
0
0
0
1
1
0
0
0
0
1
0
0
1
WRITE DATA
READ DATA
37 µs
37 µs
37 µs
37 µs
37 µs
Reads data from DDRAM, ABRAM or
CGRAM.
Arbitrator
Display Line Set
0
0
0
0
0
0
0
1
0
0
0
0
1
AS Sets the arbitrator display line.
Contrast Control
Data Write
WRITE (Contrast Data) Writes data to control the contrast of
DATA the LCD.
READ (Contrast Data) Reads data to control the contrast of
Contrast Control
Data Read
DATA
the LCD.
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
ABRAM
Address Setting
0
0
0
0
1
1
AAB
37 µs
I/D = “1” (Increment)
I/D = “0” (Decrement)
DD RAM: Display data RAM
The
S = “1” (Shifts the display.)
S/C = “1”(Shifts display.)
R/L = “1” (Right shift)
D/L = “1” (8-bit data)
N = “1” (2 lines)
execution
time is
dependent
upon
frequen-
cies.
CG RAM: Character generator RAM
ABRAM: Arbitrator data RAM
S/C = “0” (Moves the cursor.)
R/L = “0” (Left shift)
DL = “0” (4-bit data)
N = “0” (1 line)
F = “0” (5 x 7 dots)
BF = “0” (Ready to accept
an instruction)
ACG:
ADD:
CGRAM address
DDRAM address
(Corresponds to the cursor
address)
F = “1” (5 x 10 dots)
BF = “1” (Busy)
—
AAB:
ADC:
ABRAM address
B = “1” (Enables blinking)
C = “1” (Displays the cursor.)
D = “1” (Displays a character pattern.)
AS = “1” (Arbitrator Displays AS = “0” (Arbitrator Displays
Address counter (Used by
DDRAM, ABRAM and
CGRAM)
arbitrator on the
upper line)
arbitrator on the
lower line)
×: Don't Care
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