FEDL87V5002-01
OKI Semiconductor
ML87V5002
I2C Interface Timing
The internal register setting is done via I2C Interface. The interface is based on the standard mode I2C bus (SCL
frequency = 100 kHz).
Fig. 6 shows the basic timing. Table 1 summarizes the AC Characteristics of the standard mode I2C bus. Do not
change the “SDA” level as long as the “SCL” is high except the stop or start condition. Refer to the “AC
Characteristics” to know the values of timing parameters.
MSB
SDA
P
S
SCL
1
2
7
8
9
ACK
1
2
9
Start Condition
Stop Condition
tDSI2C
tDHI2C
tCCI2C
tHI2C tLI2C
Figure 6 I2C Interface Basic Timing
Table 1 AC Characteristics of Standard Mode I2C Bus (SCL Frequency = 100 kHz)
Parameter
Symbol
tRSTP
tCCI2C
tHI2C
Min.
100
10
Max.
Unit
ns
Reset Pulse Time
I2C Clock Cycle Time
I2C Clock High-Level Time
I2C Clock Low-Level Time
I2C Data Setup Time
µs
µs
µs
ns
4
tLI2C
4.7
250
0
tDSI2C
tDHI2C
I2C Data Holdup Time
3.45
µs
Power-On
For the normal operation of the ML87V5002, the pins other than the RESET pin should be maintained at a low
level until the VCC has reached the specified voltage level after powered on. Thereafter this LSI is reset by
maintaining the RESET pin at a low level for 1 ms or more. The release of the RESET level leads to starting
normal operation.
To reset this LSI during normal operation, set the RESET pin at a “L” level for a time tRSTP or more.
To power on again after powered off, verify that VCC is 0 V.
Power-on
VCC min
0V
VCC
VCC
tRSTP
1 ms (min.)
RESET
0V
Figure 7 Power-On Sequence
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