FEDL87V5002-01
OKI Semiconductor
ML87V5002
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70°C, VCC = 3.3 V ±0.3V, VSS = 0 V)
Parameter
Symbol
Condition
Min.
VCC×0.7
−0.3
Max.
5.5
Unit
V
High-level input voltage
VIH1
VIL1
VIH2
VIL2
VOH
VOL
VOL2
ILI
Low-level input voltage
VCC×0.3
5.5
V
High-level input voltage (SDA, SCL)
Low-level input voltage (SDA, SCL)
High-level output voltage
VCC×0.75
−0.3
V
VCC×0.25
V
IOH = −4 mA
IOL = 4 mA
2.4
V
Low-level output voltage
0.4
0.4
+10
+10
30
V
Low-level output voltage (SDA, INT)
Input Leakage Current
IOL = 4 mA
V
VIN = VCC or VSS
VOUT = VCC or VSS
SYSCLK = 24.576 MHz
Input pin = 0 V
−10
−10
µA
µA
mA
mA
Output Leakage Current
ILO
Supply Current (during operation)
Supply Current (during standby)
IDD1
IDD2
4.5
AC Characteristics
The SYSCLK (system clock) should be synchronized with inputs LRCK and BCK.
(Ta = 0 to 70°C, VCC = 3.3 V ±0.3V, VSS = 0 V)
Parameter
SYSCLK Cycle Time
Symbol
Condition
Min.
Max.
Unit
tSYSCLK
tSYSCKH
tSYSCKL
tBCLKI
tBCKIH
tBCKIL
tDIS
40
16
16
80
30
30
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYSCLK High-Level Time
SYSCLK Low-Level Time
BCKI Cycle Time
BCKI High-Level Time
BCKI Low-Level Time
DI Setup Time (Ext. sync. / Int. gen.)
DI Hold Time (Ext. sync. / Int. gen.)
LRCKI Setup Time
tDIH
8
tLCKIS
tLCKIH
6
LRCKI Hold Time
8
BCKO Delay Time (Ext. sync. /
Through mode)
tBCKDT
15
ns
DO Delay Time (Ext. sync. / Int. gen.)
DO Delay Time (Through Mode)
LRCKO Delay Time (Int. gen.)
tODD
tODT
CL = 20pF
CL = 20pF
CL = 20pF
−7
−7
12
15
12
ns
ns
ns
tLCKOD
LRCKO Delay Time (Ext. sync. /
Through mode)
tLCKDT
CL = 20pF
15
5
ns
Input Rise Time, Input Fall Time
Reset Pulse Time
tT
Except SDA and SCL
1
ns
ns
tRSTP
100
Note: The input voltage level is measured at VCC/0V. The confront level of the output signal is measured at VCC/2.
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