FEDL87V5002-01
OKI Semiconductor
ML87V5002
PIN DESCRIPTION
Pin
3
6
10
13
4
7
11
14
5
8
12
15
31
30
Symbol
LRCKI0
LRCKI1
LRCKI2
LRCKI3
BCKI0
BCKI1
BCKI2
BCKI3
DI0
DI1
DI2
DI3
LRCKO
BCKO
O
O
The LRCK output pin of the output interface
The polarity of LRCKO can be set by the internal register.
The BCK output pin of the output interface
In the internal generation mode, the number of BCK pulses in 1LRCK can be
set by the internal register.
29
28
27
26
20
24
22
2
DO0
DO1
DO2
DO3
SCL
SDA
INT
SYSCLK
I
I/O
O
I
The clock input pin of I
2
C (SCL)
The address data pin of I C (SDA)
The output pin for the interrupt signal to the host CPU
Open drain output
The input pin of system clock
The system clock should be synchronized with LRCKI and BCKI and the
frequency should be 128 times the sampling frequency or more.
21
20
19
18
9,17,32
1,16,25
RESET
MODE0
MODE1
MODE2
VCC
VSS
PW
PW
Power supply
Ground
I
I
The reset pin of the ML87V5002
Reset is continued while this pin is low.
I
2
C address setting pins
2
I/O
Description
The LRCK inputs of the input interface
In the 2-channel mode, LRCKI0 to LRCKI3 correspond to DI0 to DI3,
respectively.
The polarity of LRCKI can be set by the internal register.
The BCK inputs of the input interface
In the 2-channel mode, BCKI0 and BCKI3 correspond to DI0 to DI3,
respectively.
The number of BCK pulses in the 1LRCK should be 2× the number of the input
bits or more.
I
I
I
The data input pins of the input interface
The data is latched in at the rising edges of BCKI0-3.
O
The data output pins of the output interface
The data is output at the falling edge of BCKO.
Note:
The equal supply voltage should be applied to each VCC pin.
The equal supply voltage should be applied to each VSS pin.
The input pins and I/O pins are tolerant to 5 V.
The output pins support 3.3 V and should not be connected to signal lines with voltages exceeding the
supply voltage (VCC).
3/36
OKI [ OKI ELECTRONIC COMPONETS ]
