FEDL87V5002-01
OKI Semiconductor
ML87V5002
• Delay operation start/stop, interrupt mask control
SUB_ADDRESS=07h(R/W)
Table 28 Delay Operation Control Register Map
BIT6 BIT5 BIT4 BIT3 BIT2
DATA_BIT
BIT7
BIT1
BIT0
INT
AUTOR
STRT
Register Name
ENBL
MASK
WR
RD
V
V
0
V
V
0
V
V
0
0
0
0
0
0
Default Value
Table 29 Descriptions of Delay Operation Control Register Functions
Register Name Description
Controls the delay operation.
0: Stop
1: Start
ENBL
* When the CFG_ERR bit is set due to the inconsistency in the setting even if the ENBL
register is set to “1”, the delay operation is not started.
When the synchronization of LRCK and BCK is lost during the delay operation, the
ENBL register is set to “0” and the operation is suspended (AUTORSTRT = 0).
Performs resynchronization automatically when an input timing error occurs.
0: NOP
1: Automatic resynchronization
AUTORSTRT
INT_MASK
* When this register is set to “1”, the INT output is fixed to a “H” level even if the
INT_MASK is “0” except when the delay operation is suspended by CFG_ERR.
However, the error statuses which cause interrupts are set.
Masks interrupt outputs.
0: NOP
1: Mask
* When this register is set to “1”, the error statuses which cause interrupts are masked
though the INT output is fixed to a “H” level.
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