FEDL87V5002-01
OKI Semiconductor
ML87V5002
• CH delay value setting register
CH0(DO0 Lch)
CH0(DO0 Lch)
CH1(DO0 Rch)
CH1(DO0 Rch)
CH2(DO1 Lch)
CH2(DO1 Lch)
CH3(DO1 Rch)
CH3(DO1 Rch)
CH4(DO2 Lch)
CH4(DO2 Lch)
CH5(DO2 Rch)
CH5(DO2 Rch)
CH6(DO3 Lch)
CH6(DO3 Lch)
CH7(DO3 Rch)
CH7(DO3 Rch)
Delay Value Setting (Lower-order 8 bits)
SUB_ADDRESS=10h(R/W)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
Delay Value Setting (Lower-order 8 bits)
Delay Value Setting (Higher-order 8bits)
SUB_ADDRESS=11h(R/W)
SUB_ADDRESS=12h(R/W)
SUB_ADDRESS=13h(R/W)
SUB_ADDRESS=14h(R/W)
SUB_ADDRESS=15h(R/W)
SUB_ADDRESS=16h(R/W)
SUB_ADDRESS=17h(R/W)
SUB_ADDRESS=18h(R/W)
SUB_ADDRESS=19h(R/W)
SUB_ADDRESS=1ah(R/W)
SUB_ADDRESS=1bh(R/W)
SUB_ADDRESS=1ch(R/W)
SUB_ADDRESS=1dh(R/W)
SUB_ADDRESS=1eh(R/W)
SUB_ADDRESS=1fh(R/W)
Table 36 CH Delay Value Setting (Lower-Order 8 Bits) Register Map
DATA_BIT
Register Name
WR
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DLYx_L
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
RD
Default Value
Table 37 CH Delay Value Setting (Higher-Order 8 Bits) Register Map
DATA_BIT
Register Name
WR
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DLYx_H
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
RD
Default Value
Table 38 Description of the CH Delay Value Setting Register Function
Register Name Description
Sets the delay time.
The delay time is controlled in units of FS and set in a 16-bit length (DLYx_H =
higher-order 8 bits / DLYx_L = lower-order 8 bits).
* 2-ch mode
When the input data length = 16 bits, the maximum delay is 65535.
When the input data length > 16 bits, the maximum delay is 32767.
* 8-ch mode
DLYx_H[7:0]
DLYx_L[7:0]
When the input data length = 16 bits, the maximum delay is 16383.
When the input data length > 16 bits, the maximum delay is 8191.
When the value is set to reduce the maximum delay time (for example, 2-ch mode is
changed to 8-ch mode), the maximum value is adopted as the delay value for the
channel value which exceeds the maximum value. However, the value read from the
register is the current value set, not the value limited with the maximum delay value.
x = 0, 1, 2, 3, 4, 5, 6, 7
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