FEDL87V5002-01
OKI Semiconductor
ML87V5002
• Output data mask control
SUB_ADDRESS=0ah(R/W)
Table 34 Output Data Mask Register Map
DATA_BIT
Register Name
WR
BIT7
BIT6
BIT5
BIT4
BIT3
MASK
BIT2
BIT1
BIT0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
RD
Default Value
Table 35 Descriptions of the Output Data Mask Register Function
Register Name
Description
Controls the output masking (output data = all “0”).
0: No masking (data is output).
1: Masking.
MASK
* When this bit is set to '1' during the delay operation, the output data of the selected
channel is set to '0' synchronized to LRCK. When the bit is set to '0' during the delay
operation, the output masking is released synchronized to LRCK.
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