PEDL87V21071-01
OKI Semiconductor
ML87V21071
2.2.4 Memory Control Setting 2 (phase adjustment)
SUB_ADDRESS = 44h(W/R): Input system memory control vertical phase adjustment setting
DATA_BIT
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
NPVWE
2
BIT1
BIT0
0
Register name
INPR
(Reserved) (Reserved)
4
3
1
SUB_ADDRESS = 45h(W/R): Input system memory control horizontal phase adjustment setting
DATA_BIT
BIT7
BIT6
BIT5
BIT4
NPHWE
4
BIT3
BIT2
2
BIT1
1
BIT0
0
Register name
7
6
5
3
NPVWE[4:0] Initial value: 1000; Setting range: 00001 to 11111
When INSINV = 0, sets the number of lines (IHS input count) from the IVS fall position up to the
vertical standard write start position.
When IVSINV = 1, the number of lines is set from the IVS rise position.
NPVWE[4]is enabled only when INPR = 1.
INPR
Initial value: 0; Setting range: 0 to 1
Sets progressive input.
Table R2-2-4 Progressive Input Setting
INPR
Input
0
Interlace (525i/625i)
Progressive input (525p/625p)
1
NPHWE[7:0] Initial value: 1000_0000; Setting range: 0000_0001 to 1111_1111
When IHSINV = 0, sets the number of pixels from the IHS rise position up to the horizontal standard
write start position.
When IHSINV = 1, sets the number of pixels from the IHS fall position.
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