PEDL87V21071-01
OKI Semiconductor
ML87V21071
2.2.2 Input System Memory Control Mode Setting
SUB_ADDRESS = 42h(W/R): Input system memory control mode setting
DATA_BIT
BIT7
BIT6
BIT5
BIT4
BIT3
IFLS
BIT2
BIT1
BIT0
Register name FCON (Reserved) (Reserved) IVEM
IFINV
IHSINV IVSINV
IVSINV Initial value: 0; Setting range: 0 to 1
Sets input polarity (timing edge) of input system vertical synchronization signal (IVS).
The IC operates with the fall of IVS positive polarity as a reference. However, in case the IVS input is of
negative polarity, it is possible to match the polarity reference such as the rise of positive polarity.
Table R2-2-2 (1) IVS Input Polarity (Edge) Setting
IVSINV
IVS input polarity 1
Positive polarity (Fall)
Negative polarity (Rise)
IVS input polarity 2
Negative polarity (Fall)
Positive polarity (Rise)
0
1
IHSINV Initial value: 0; Setting range: 0 to 1
Sets input polarity (timing edge) of input system horizontal synchronization signal (IHS).
The IC operates with the rise of IHS positive polarity as a reference. However, if the IHS input is of
negative polarity, it is possible to match the polarity reference such as making the fall of positive
polarity.
Table R2-2-2 (2) IHS Input Polarity (Edge) Setting
IHSINV
IHS input polarity 1
Positive polarity (Rise)
Negative polarity (Fall)
IHS input polarity 2
Negative polarity (Rise)
Positive polarity (Fall)
0
1
IFINV Initial value: 0; Setting range: 0 to 1
Sets the polarity of input system detection field pulse.
Table R2-2-2 (3) Polarity Setting of Input System Detection Field Pulse
IFINV
Detection field pulse
Decision result
0
1
Decision result inversion
IFLS Initial value: 0; Setting range: 0 to 1
Sets input system field decision mode selection.
Table R2-2-2 (4) Input System Field Decision Mode Selection Setting
IFLS
Detection field pulse
IHS decision
0
1
0.5H pulse decision
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