PEDL87V21071-01
OKI Semiconductor
ML87V21071
ICINV Initial value: 0; Setting range: 0 to 1
Sets internal input system clock (IICLK) polarity.
Sets the polarity of IICLK (ICLK frequency-divided by 2) generated in the input 8-bit mode and ITU-R
BT.656 mode.
This setting is not in synchronization with IVS.
Table R2-2-1 (3) IICLK Polarity Setting
ICINV
IICLK polarity
0
1
At IHS rise reset: 1
At IHS rise reset: 0
IHES Initial value: 0; Setting range: 0 to 1
Sets IHS edge for internal input system clock (IICLK) reset
Selects the reset timing of IICLK generated in 1H period at the fall or rise of IHS.
Table R2-2-1 (4) IHS Edge Setting for IICLK Reset
IHES
IHS edge for H reset
0
Rise
1
Fall
POFF Initial value: 0; Setting range: 0 to 1
Sets ITU-R BT.656 mode parity check.
Table R2-2-1 (5) ITU-R BT.656 Mode Parity Check Setting
POFF
Parity check
ON
0
1
OFF
HBLKM Initial value: 0; Setting range: 0 to 1
Sets an ITU-R BT.656 mode timing reference mask.
Invalid timing reference codes of horizontal blanking (between EAV and SAV) are ignored.
Table R2-2-1(6) Timing Reference Code Mask Setting
HBLKM
Timing reference code detection
All timing reference code enabled.
0
1
Timing reference code during horizontal blanking period disabled.
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