PEDL87V21071-01
OKI Semiconductor
ML87V21071
Input sync signal phase 1
Field A input
Input sync signal phase 3
Field A input
IHS
IVS
IHS
IVS
0
1
2
n-1
n
0
1
2
3
4
5
n-1
n
#IVR
#IF
#IVR
#IF
Field B input
Field B input
IHS
IVS
IHS
IVS
0
1
2
n-1
n
0
1
2
3
4
5
n-1
n
#IVR
#IF
#IVR
#IF
Input sync signal phase 2
Field A input
Input sync signal phase 4
Field A input
IHS
IVS
IHS
IVS
0
1
2
n-1
n
0
1
2
3
4
5
n-1
n
#IVR
#IF
#IVR
#IF
Field B input
Field B input
IHS
IVS
IHS
IVS
0
1
2
n-1
n
n+1
0
1
2
3
4
5
n-1
n
n+1
#IVR
#IF
#IVR
#IF
Figure F1-1-6 Input System Vertical Reset Compensation by IVEM Setting
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