PEDL87V21071-01
OKI Semiconductor
ML87V21071
Input in 16-bit mode
ICLK
Input in 8-bit mode or ITU-R BT.656 mode
ICLK
#IICLK
YI[7:0]
CI[7:0]
#IICLK
Yn
Cn
Yn+1
Cn+1
Yn+2
Cn+2
Yn+3
Cn+3
Cbn
Yn
Crn
Yn+1
YI[7:0]
CI[7:0]
don't care (no connect)
#: Internal signal
Figure F1-2-1 (1) Input Data Timing
The data and control signal interfaces according to input system modes are as follows.
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•
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Input in 16-bit mode
Vertical Sync. signal:
Horizontal Sync. signal:
Data input pin:
Input system clock frequency: fICLK = 12.2727272/13.5/14.31818/14.75 MHz
Clip level:
IVS
IHS
YI[7:0], CI[7:0] (YCbCr-4:2:2)
None
Input in 8-bit mode
Vertical Sync. signal:
Horizontal Sync. signal:
Data input pin:
Input system clock frequency: fICLK = 24.545454/27/28.63636/29.5 MHz
Clip level:
IVS
IHS
YI[7:0], (YCbCr-4:2:2)
None
ITU-R BT.656 mode
Vertical Sync. signal:
Horizontal Sync. signal:
Data input pin:
SAV, EAV split
SAV, EAV split
YI[7:0] (YCbCr-4:2:2)
Input system clock frequency: fICLK = 27 MHz
Clip level:
00h → 01h, FFh → Feh
* By setting POFF (SUB:41h-bit[6]) to 1, the parity bits of SAV and EAV can be disabled.
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