PEDL87V21071-01
OKI Semiconductor
ML87V21071
DC Characteristics
(Ta = 0 to 70°C)
Parameter
Symbol
VIH1
Condition
Min.
Max.
Unit
V
V
DD+0.3
“H” level input voltage
“L” level input voltage
—
—
V
DD × 0.7
–0.3
V
VIL1
V
DD × 0.3
“H” level input voltage
(TEST1–TEST7, TESTM, SELF)
“L” level input voltage
(TEST1–TEST7, TESTM, SELF)
“H” level input voltage
(SDA, SCL, IVS, IHS, RESET)
“L” level input voltage
(SDA, SCL, IVS, IHS, RESET)
VIH2
VIL2
VIH3
VIL3
—
VDD+0.3
V
V
V
V
V
DD × 0.75
–0.3
—
VDD × 0.25
Schmitt
Schmitt
VDD+0.3
V
DD × 0.75
–0.3
VDD × 0.25
“H” level input current (pull-down)
IIH
IIL
50 kΩ pull down
—
20
–10
2.4
0
200
+10
VDD
0.4
µA
µA
V
Input leakage current
“H” level output voltage (other than SDA)
“L” level output voltage (other than SDA)
“L” level output voltage (N-Ch. OD)
(SDA)
VOH
VOL
IOH = –4 mA
IOL = 4 mA
V
VOOL
IOL
IOL = 4 mA
0
0.4
V
0 ≤ Vout ≤ VDD
Output leakage current
–10
+10
µA
Output disabled
ICLK: 29.5MHz
Output disabled
Input pin = 0 V
Supply current (during operation)
Supply current (during standby)
IDD1
IDD2
—
—
100 (TBD)
5
mA
mA
AC Characteristics
(Ta = 0 to 70°C)
Parameter
ICLK clock cycle time
ICLK clock duty ratio
ICLK input set-up time
ICLK input hold time
ICLK output delay time
Symbol
tICLK
dtICLK
tIISU
Condition
Min.
33
40
5
Max.
Unit
ns
%
—
—
60
—
—
25
25
17
17
—
—
—
ns
ns
ns
tIIH
3
tIOD
CL = 30pF
2
CL = 30 pF (IICLK output)
CL = 30 pF (ICLK output)
CL = 30 pF
2
CLKO delay time
Data through time
tCKD
ns
ns
2
tDIDO
2
Note 1: Measurement conditions
Output comparison level: VOH = VDD/2, VOL = VDD/2
Input voltage level: VIH = VDD, VIL = 0.0 V
Note 2: Input/output data for the internal memory is guaranteed from the third input-system vertical synchronization
signal with RESET = 1 after VDD reaches 3.0 V after the power is turned on. (Due to memory initialization,
the first and second data for two fields is not guaranteed.)
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