FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 4 (Three-Way Calling: Terminal Side [Two Parties] – NW Side [One Party])
GSX1
AIN1N
TXGAIN_PCM1
RX_SIG
PCM_TXEN1
TXDETB
10kΩ
PCM I/F
Encoder
G.711
A/D1
BPF
LPEN0
TXGAINB
STGAINB
CODECB_TXEN
AMP1
P/S
TXGAIN_PCM0 PCM_TXEN0
PCMO
SYNC
BCLK
Linear PCM
Codec (CODEC_B)
TS
CONT
PCM Codec
CLKSEL
RXGAIN_ITS1
Decoder
G.711
10kΩ
PCMI
RXGAINB
S/P
CODECB_RXEN
LPEN1
D/A1
A/D0
LPF
BPF
VFRO1
AMP3
RXGENB
RXGAIN_ITS2
RXGAIN_PCM0
PCM_RXEN0
RXGAIN_PCM1
PCM_RXEN1
GSX0
AIN0N
AIN0P
TXGEN
TXDETA
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
FR0B
WRB
RDB
10kΩ
G.729.A
TX
Buffer0
TXGAIN_SC
CH1
T
TXGAIN
CH1
SC_TXEN
S
TXGAINA
STGAINA
CODECA_TXEN
Sin
Encoder
G.711
AMP0
Sout
GPAD
+
LPAD
Center
Clip
W
TX
Buffer1
-
ATTs
CH2
DC_EN
TXGAIN
RX2TX1
_GAIN
_CH2
Linear PCM
Codec (CODEC_A)
Echo Canceller
Bus Control
Unit
AFF
RX1TX2
Speech Codec
_GAIN
CSB
D0-D15
A0-A7
10kΩ
16b
8b
RXGAIN
G.729.A
RX
RXGAINA
RXGAIN_SC
SC_RXEN
Rout
ATTr
Rin
_CH1
Buffer0
T
S
W
D/A0
LPF
VFRO0
AVREF
Decoder
G.711
CH1
CH2
CODECA_RXEN
RXGENA
RXGAIN
_CH2
AMP2
RX
Buffer1
RXGEN
RXDET
RX_SIG
DC_EN
VREF
Frame/DMA
Controller
TIMER
TIMOVF
GPIO2
Generator path
TGEN1_EXFLAG
TONE_GEN1
(TONE C/D)
TGEN0_EXFLAG
Detector path setting
TXDETA
FDET_RQ
DVDD2
DVDD1
DVDD0
DGND2
DGND1
DGND0
DPGEN
DPDET
TXGEN
FSK_DET
FDET_FER/FDET_OER
Control
Register
TXDETB
FDET_D[7:0]
RXGENA_EN
RXGENB_EN
GPIO0
DTMF_DET
DTMF_REC
RXGENA
RXGENB
DP_DET
DTMF_CODE[3:0]
TONE_GEN0
(TONE A/B)
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
TONE_DET0
TONE_DET1
TONE0_DET
TONE1_DET
FGEN_FLAG
RXGEN
POWER
MCK
SYNC (8 kHz)
PLL
CKGN
FSK_GEN
INT
INTB/
GPIOA[6]
AGND
AVDD
RXDET
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288 MHz
FGEN_FLAG
VREGOUT
VGB
TIMOVF
Unused
8
6
4
32/42
OKI [ OKI ELECTRONIC COMPONETS ]
