FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 5 (Three-Way Calling: Terminal Side [One Party] – NW Side [Two Parties])
GSX1
AIN1N
TXGAIN_PCM1
RX_SIG
PCM_TXEN1
TXDETB
10kΩ
PCM I/F
Encoder
G.711
A/D1
BPF
LPEN0
TXGAINB
CODECB_TXEN
AMP1
P/S
TXGAIN_PCM0
PCM_TXEN0
PCMO
SYNC
BCLK
Linear PCM
Codec (CODEC_B)
TS
CONT
PCM Codec
STGAINB
CLKSEL
RXGAIN_ITS1
Decoder
G.711
10kΩ
RXGAINB
PCMI
S/P
CODECB_RXEN
LPEN1
D/A1
A/D0
LPF
BPF
VFRO1
AMP3
RXGENB
RXGAIN_ITS2
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN1
PCM_RXEN0
GSX0
AIN0N
AIN0P
TXGEN
TXDETA
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
10kΩ
TXGAIN_SC
G.729.A
TXGAIN
TX
Buffer0
T
S
W
CH1
SC_TXEN
TXGAINA
CODECA_TXEN
Sin
Encoder
G.711
AMP0
Sout
GPAD
LPAD
+
Center
Clip
ATTs
TX
Buffer1
-
CH2
FR0B
WRB
RDB
CSB
DC_EN
RX2TX1
_GAIN
TXGAIN
_CH2
Linear PCM
Codec (CODEC_A)
Echo Canceller
Bus Control
Unit
AFF
RX1TX2
Speech Codec
STGAINA
RXGAINA
_GAIN
D0-D15
A0-A7
10kΩ
RXGAIN
_CH1
16b
8b
G.729.A
RX
Buffer0
RXGAIN_SC
Rout
Rin
ATTr
T
S
W
D/A0
LPF
VFRO0
AVREF
Decoder
G.711
CH1
CODECA_RXEN
RXGENA
SC_RXEN
RXDET
RXGAIN
_CH2
RX
Buffer1
AMP2
RXGEN
CH2
DC_EN
RX_SIG
VREF
Frame/DMA
Controller
TIMER
TIMOV
Generator path
TGEN1_EXFLAG
TONE_GEN1
(TONE C/D)
TGEN0_EXFLAG
Detector path setting
TXDETA
FDET_RQ
GPIO
DVDD2
DVDD1
DVDD0
DPGEN
DPDET
FSK_DET
FDET_FER/FDET_OER
TXGEN
Control
Register
TXDETB
FDET_D[7:0]
RXGENA_EN
RXGENB_EN
DTMF_DET
GPIO
DTMF_REC
RXGENA
RXGENB
DTMF_CODE[3:0]
DP
D
DTMF_DET
TONE_GEN0
(TONE A/B)
DGND2
DGND1
DGND0
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
TONE_DET0
TONE_DET1
TONE0_DET
TONE1_DET
POWER
MCK
SYNC (8 kHz)
FGEN_FLAG
CKGN
RXGEN
PLL
INT
FSK_GEN
INTB/
AGND
RXDET
FDET_RQ
GPIOA[6]
FDET_FER/FDET_OER
AVDD
OSC
12.288 MHz
FGEN_FLAG
VREGOUT
TIMOVF
Unused
VGB
8
6
4
This example shows the configuration for making three-way calling between the terminal side (one party) and
VoIP NW side (two parties).
RX_SIG
Linear
PCM
PCM
I/F
PCM
Codec
Codec
(CODEC_B)
Linear
PCM
VoIP-NW1
VoIP-NW2
A-TEL
Speech
Codec
MCU
I/F
EC
Codec
(CODEC_A)
RX_SIG
ML7204 (Configuration example 5)
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