FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 7 (CODEC-A-CODEC-B Loop Back Mode)
GSX1
AIN1N
PCM_TXEN1
TXGAIN_PCM1
TXDETB
RX_SIG
10kΩ
PCM I/F
Encoder
G.711
A/D1
BPF
LPEN0
TXGAINB
STGAINB
CODECB_TXEN
AMP1
TXGAIN_PCM0 PCM_TXEN0
P/S
PCMO
SYNC
BCLK
Linear PCM
Codec (CODEC_B)
TS
CONT
PCM Codec
CLKSEL
RXGAIN_ITS1
Decoder
G.711
10kΩ
PCMI
RXGAINB
S/P
CODECB_RXEN
LPEN1
D/A1
A/D0
LPF
BPF
VFRO1
GSX0
AMP3
RXGAIN_ITS2
RXGENB
RXGAIN_PCM0
RXGAIN_PCM1
PCM_RXEN1
PCM_RXEN0
TXGEN
TXDETA
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
10kΩ
G.729.A
TX
Buffer0
TXGAIN_SC
SC_TXEN
AIN0N
AIN0P
CH1
T
TXGAIN
_CH1
S
TXGAINA
STGAINA
CODECA_TXEN
Sin
Encoder
G.711
AMP0
Sout
GPAD
LPAD
+
Center
Clip
W
TX
Buffer1
-
ATTs
CH2
FR0B
WRB
RDB
CSB
DC_EN
TXGAIN
RX2TX1
_GAIN
_CH2
Linear PCM
Codec (CODEC_A)
AFF
Echo Canceller
Bus Control
Unit
RX1TX2
Speech Codec
_GAIN
D0-D15
A0-A7
10kΩ
RXGAIN
_CH1
16b
8b
G.729.A
RX
Buffer0
Rout
Rin
RXGAIN SC
SC_RXEN
RXGAINA
ATTr
T
D/A0
LPF
S
VFRO0
AVREF
Decode
G.711
CH1
CODECA_RXEN
RXGENA
RXGAIN
CH2
W
RX
Buffer1
AMP2
RXGEN
RXDET
RX_SIG
CH2
DC_EN
VREF
Frame/DMA
Controller
TIMER
TIMOVF
Generator path
TGEN1_EXFLAG
TONE_GEN1
Detector path setting
TXDETA
GPIO2
FDET_RQ
DPGEN
DPDET
DVDD2
DVDD1
DVDD0
DGND2
DGND1
DGND0
FSK_DET
TXGEN
FDET_FER/FDET_OER
Control
Register
TXDETB
(TONE C/ D)
FDET_D[7:0]
RXGENA_EN
RXGENB_EN
GPIO0
DTMF DET
DTMF_REC
RXGENA
RXGENB
TGEN0_EXFLAG
DP_DET
DTMF_CODE[3:0]
TONE_GEN0
(TONE A/ B)
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
TONE_DET0
TONE_DET1
TONE0_DET
TONE1_DET
FGEN_FLAG
RXGEN
POWER
MCK
SYNC (8 kHz)
CKGN
PLL
FSK_GEN
INT
INTB/
GPIOA[6]
RXDET
AGND
AVDD
FDET RQ
FDET_FER/FDET_OER
OSC
12.288 MHz
FGEN_FLAG
TIMOVF
VREGOUT
VGB
Unused
8
6
4
This example shows the configuration where CODEC_A and CODEC_B are connected in loopback mode
according to the internal path settings.
RX_SIG
Linear
PCM
PCM
I/F
PCM
B
Codec
Codec
(CODEC_B)
Linear
PCM
A
Speech
Codec
MCU
I/F
EC
Codec
(CODEC_A)
RX_SIG
ML7204 (Configuration example 7)
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