FEDL7033-02
ML7033
1
Semiconductor
Table 1 PCM Codes in 8-bit PCM Mode with the LIN (CR0-B3) bit = “0”
PCMIN/PCMOUT
ALAW (CR0-B2) bit = “0” (µ-law ) ALAW (CR0-B2) bit = “1” (A-law )
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
INPUT/OUTPUT
Level
+Full scale
+0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
–0
–Full scale
Table 2 PCM Codes in 14-bit Linear PCM Mode with the LIN (CR0-B3) bit = “1”
PCMIN/PCMOUT
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
INPUT/OUTPUT
Level
+Full scale
0
0
0
1
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
+1
0
–1
–Full scale
PDN
Power-down control signal. When PDN is a asserted (logic “0”), both the channel 1 and channel 2 circuits enter
the power-down state. However, even in power-down mode, the state of the control registers is maintained.
Reads and writes to the registers are also possible, and the state of the INT pin also changes in accordance with
inputs from the SLIC devices. This pin is deasserted (logic “1”) by external logic during normal operation.
This power-down function is available even in power saving mode by the MODEn (CR0-B1/CR0-B0) bit.
RESET
An input to reset control registers. By asserting the RESET pin (applying a logic “0”), all control registers are
initialized. During a normal operation mode, set this pin logic “1”.
Table 3 State of PCMOUT in 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
PDN pin
MODE1 bit
0/1
MODE0 bit
0/1
ALAW bit
CH2 PCM Data
Hi-Z *1
CH1 PCM Data
Hi-Z *1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
Operate
0
0/1
0
1
0
1
0
1
0
1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
Operate
1
1
1
1
0
0
1
1
0
1
0
1
Operate
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
Operate
Operate
Operate
Operate
Operate
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