FEDL7033-02
ML7033
1
Semiconductor
FUNCTIONAL DESCRIPTION
Pin Functional Description
AIN1N, AIN1P, AIN2N, AIN2P, GSX1, GSX2
The AINnN and AINnP pins are the transmit path analog inputs for Channel-n, where n equals channel 1 or
channel 2. The AINnN pin is the inverting input, and the AINnP pin is the non-inverting input for the op-amp.
The GSXn pin functions as the transmit path level adjustment for Channel-n and is connected to the output of the
op-amp. It is used to adjust the output level as shown in Figure 8 below.
When the AINnN or AINInP pins are not in use, connect the AINnN pin to the GSXn pin and the AINnP pin to
the SGC pin. During power-down mode, the GSXn output is in a high impedance state.
In the case of the analog input 2.226 Vpp at the GSXn pin, the digital output will be +3.00 dBm0.
GSX1
CH1 Gain
Gain = R2/R1 ≤ 10
R1: Variable
R2
AIN1N
AIN1P
CH1
Analog
Input
R2 > 20 kΩ
C1 R1
C1 > 1/(2 × 3.14 × 30 × R1)
SGC
CH2 Gain
Gain = R4/R3 ≤ 10
R3: Variable
GSX2
R4
AIN2N
AIN1P
R4 > 20 kΩ
CH2
C2 > 1/(2 × 3.14 × 30 × R3)
Analog
Input
C2 R3
SGC
Figure 8 Example of Analog Input Setting Schematic
AOUT1P, AOUT1N, AOUT2P, AOUT2N
The AOUTnN and AOUTnP pins are the receive path analog outputs from Channel-n, where n equals channel 1
or channel 2. These pins can drive a load of 20 kΩ or more. When the AOUTnSEL register bit (CR7-B7/CR14-
B7) is cleared (0), the AOUTnP pin is a single-ended output from Channel-n and the AOUTnN pin is at high
impedance. When the AOUTnSEL bit is set (1), the AOUTnN and AOUTnP pins are differentials outputs from
the corresponding channel.
The output signal from each of these pins has an amplitude of 3.4 Vpp above and below the signal ground
voltage (SG). Hence, when the maximum PCM code (+3.00 dBm0) is input to the PCMIN pin, the maximum
amplitude between the AOUTnN pin and the AOUTnP pin will be 6.8 Vpp.
While the device is in power-down mode, or the corresponding channel (1 or 2) is in power saving mode, the
related outputs are high impedance. Refer to Table 5 for more information.
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