PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (7)
Memory to ML60851C (Demand Transfer, Single Address Mode)
Parameter
DREQ Disable Time
FIFO Access Time
Symbol
Condition
Load 20 pF
FIFO WRITE
Min.
—
42
0
Max.
20
Unit
ns
Note
t1
t2
t3
t4
t5
—
ns
1
DACK Hold Time
—
ns
Write Data Setup Time
Write Data Hold Time
30
2
—
ns
—
ns
8-bit DMA
63
105
—
ns
2
3
Recovery Time
t6
16-bit DMA
—
ns
Notes: 1. When in Single Address mode, A7:A0 and CS are ignored.
t is defined depending on DACK or WR which becomes active last.
2
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
DACK
t2
t6
t3
WR
(Note)
t4
t5
Last Packet Write
DIN
(Note) ThelastWritetoreachthebytesize(maximumpacketsize)specifiedbytheEP1Payload
Register.
ToterminateDMAtransferbeforereachingthemaximumpacketsize,setEP1PacketReady
by writing "1" to the EP1 Endpoint Packet Ready bit.
58/67
OKI [ OKI ELECTRONIC COMPONETS ]
