PEDL60851C-02
ML60851C
¡ Semiconductor
Application Interface
Signal
Type Assertion
Description
Upper byte (MSB) of data bus. This data bus is used by applications to access
register files and FIFO data.
D15:D8
I/O
I/O
—
—
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
Address when ADSEL is LOW. This address signal is used by application to
access register files and FIFO data.
AD7:AD0
A7:A0
I
—
This signal is ignored (all lows or all highs) when ADSEL is HIGH.
Chip Select. When this signal is asserted LOW, the ML60851C is selected
and ready to read or write data.
CS
RD
I
I
LOW
LOW
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
WR
I
LOW
LOW
Interrupt Request. When this signal is asserted, the ML60851C makes an
INTR
DREQ
DACK
ALE
O
O
I
(Note 1) interrupt request to the application.
LOW
(Note 1)
HIGH
DMA Request. This signal requests the Endpoint FIFO to make a DMA transfer.
DMA Acknowledge Signal. This signal, when asserted, enables accessing
(Note 1) FIFOs, without address bus setting.
When ADSEL is HIGH, the address and CS on AD7:AD0 is latched at the
trailing edge of this signal. This signal is ignored when ADSEL is LOW.
I
—
When ADSEL is LOW, the address is input on A7:A0 and data is input on
D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of
address and data are multiplexed on AD7:AD0.
ADSEL
I
I
—
System Reset. When this signal is asserted LOW, the ML60851C is reset.
When the ML60851C is powered on, this signal must be asserted for 1 ms or more.
RESET
LOW
Note: 1. Initialvalueimmediatelyafterresetting. Itsassertioncanbechangedbyprogramming.
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OKI [ OKI ELECTRONIC COMPONETS ]
