PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (5)
Memory to ML60851C (Single Transfer, Single Address Mode)
Parameter
DREQ Disable Time
DREQ Enable Time
FIFO Access Time
Symbol
Condition
Min.
—
—
42
0
Max.
20
Unit
ns
Note
t1
t2
t3
t4
t5
t6
Load 20 pF
63
ns
4
1
FIFO WRITE
—
ns
DACK Hold Time
—
ns
Write Data Setup Time
Write Data Hold Time
30
2
—
ns
—
ns
8-bit DMA
63
105
—
ns
2
3
Recovery Time
t7
16-bit DMA
—
ns
Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t by setting the DMA interval register (DMAINTVL).
2
DREQ
t1
t4
t2
DACK
t3
t7
WR
t6
t5
DIN
56/67
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