PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (3)
ML60851C to Memory (Demand Transfer, Single Address Mode)
Parameter
DREQ Disable Time
DACK Hold Time
Symbol
Condition
Min.
—
0
Max.
20
Unit
ns
Note
t1
t2
t3
t4
Load 20 pF
—
ns
Read Data Delay Time
Data Hold Time
Load 20 pF
Load 20 pF
8-bit DMA
16-bit DMA
—
0
25
ns
1
25
ns
63
105
—
ns
2
3
Recovery Time
t5
—
ns
Notes: 1. When in Single Address mode, t is defined depending on DACK orRD which becomes
3
active last.
A7:A0 and CS are ignored.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
DACK
t5
t2
RD
t3
t4
Last Packet Read
DOUT
54/67
OKI [ OKI ELECTRONIC COMPONETS ]
