PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (8)
Memory to ML60851C (Demand Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
FIFO Access Time
CS Hold Time
Symbol
Condition
Load 20 pF
FIFO WRITE
Min.
—
42
0
Max.
20
Unit
ns
Note
t1
t2
t3
t4
t5
—
ns
1
—
ns
Write Data Setup Time
Write Data Hold Time
30
2
—
ns
—
ns
8-bit DMA
63
105
—
ns
2
3
Recovery Time
t6
16-bit DMA
—
ns
Notes: 1. When in Dual Address mode, the DACK is ignored.
A7:A0 specifies the FIFO address.
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
t is defined depending on CS or WR which becomes active last.
2
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
CS
t1
t3
t2
t6
WR
(Note)
t4
t5
Last Packet Write
DIN
(Note) Refer to the previous page.
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