PEDL60851C-02
1
Semiconductor
ML60851C
EP0 Receive packet ready bit (D0)
This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D0 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
Asserting condition
Action when asserted
EP0 Receive packet ready (D0)
1. When data is received in EP0
and storing of one packet of
receive data in EP0RXFIFO is
completed.
EP0 is locked (that is, an NAK is
returned automatically when a data
packet is received from the host
computer).
2. When a setup packet is received (In the case of the asserting
during a control Read or a control condition 1, the local MCU can read
Write transfer.
EP0RXFIFO.)
Bit name
Deasserting condition
1. When the local MCU resets
(writes a “1” in) this bit.
Action when deasserted
Reception is possible in EP0.
EP0 Receive packet ready (D0)
2. When the local MCU resets the
setup ready bit during a control
Write transfer.
R/Reset: Reading possible/ Reset when a “1” is written
R/Set: Reading possible/ Set when a “1” is written
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