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ML60851C 参数 Datasheet PDF下载

ML60851C图片预览
型号: ML60851C
PDF下载: 下载PDF文件 查看货源
内容描述: USB设备控制器 [USB Device Controller]
分类和应用: 控制器
文件页数/大小: 67 页 / 424 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL60851C-02  
1
Semiconductor  
ML60851C  
End Point Packet Ready Register (PKTRDY)  
This register indicates whether or not the preparations for reading out or writing in a packet data have been  
completed. In addition, this register is also used for controlling the handshake packet (ACK/NAK)  
Read address  
Write address  
C8h  
48h  
D7  
0
D6  
0
D5  
0
D4  
0
D3  
0
D2  
0
D1  
0
D0  
0
After a hardware reset  
After a bus reset  
Definition  
0
0
0
0
0
0
0
0
0
EP0 Receive packet ready (R/Reset)  
EP1 Receive packet ready (R/Reset)  
EP2 Receive packet ready (R/Reset)  
EP0 Transmit packet ready (R/Set)  
EP1 Transmit packet ready (R/Set)  
EP2 Transmit packet ready (R/Set)  
EP3 Transmit packet ready (R/Set)  
This is the register for indicating that the local MCU can request a read/write of the FIFO for each EP. The logical  
sums (AND) of each of these bits and the corresponding bits of INTENBL become the bits of INTSTAT.  
The ML60851C asserts a receive packet ready bit (set to “0”) and generates an interrupt cause. The local MCU  
resets the receive packet ready bit after completion of the interrupt servicing (such as taking out data from the  
corresponding receive FIFO, etc.,).  
The ML60851C deasserts a transmit packet ready bit and generates an interrupt cause. The local MCU sets the  
receive packet ready bit after completion of the interrupt servicing (such as writing data in the corresponding  
transmit FIFO, etc.,).  
The bit D3 is fixed at “0”, and even if a “1” is written in this bit, that write operation will be invalid.  
The operations of the different bits of PKTRDY are described in detail below.  
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