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ML60851C 参数 Datasheet PDF下载

ML60851C图片预览
型号: ML60851C
PDF下载: 下载PDF文件 查看货源
内容描述: USB设备控制器 [USB Device Controller]
分类和应用: 控制器
文件页数/大小: 67 页 / 424 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL60851C-02  
1
Semiconductor  
ML60851C  
Packet Error Register (PKTERR)  
Read address  
Write address  
C2h  
D7  
0
D6  
0
D5  
0
D4  
0
D3  
0
D2  
0
D1  
0
D0  
0
After a hardware reset  
After a bus reset  
Definition  
0
0
0
0
0
0
0
0
0
0
0
0
Bit stuff error (R)  
Data CRC error (R)  
Address CRC error (R)  
PID Error (R)  
Each bit is asserted when the corresponding error occurs and is deasserted when SOP is received.  
This register is used to report the error information. This register is useful for the tests during development, or for  
preparing the error frequency measurement report. This register is not particularly required for the specification of  
commercial a product.  
FIFO Status Register 1 (FIFOSTAT1)  
Read address  
Write address  
C3h  
D7  
0
D6  
0
D5  
0
D4  
0
D3  
1
D2  
0
D1  
1
D0  
0
After a hardware reset  
After a bus reset  
Definition  
0
0
0
0
1
0
1
0
0
0
0
0
Receive FIFO0 Full (R)  
Receive FIFO0 Empty (R)  
FIFO1 Full (R)  
FIFO1 Empty (R)  
This register reports the statuses of the EP0RXFIFO and the FIFO for EP1. Normally, there is no need to read this  
register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.  
Receive FIFO0 Full:  
This bit becomes “1” when 8-bytes of data are stored in the EP0RXFIFO. This bit is  
not set to “1” when a packet less than 8 bytes long (a short packet) is stored in.  
Receive FIFO0 Empty: This bit will be “1” when the EP0RXFIFO0 is empty.  
FIFO1 Full:  
This bit becomes “1” when 64 bytes of data is stored in the FIFO for EP1. This is true  
during both transmission and reception. This bit does not become “1” in the case of a  
short packet. The FIFO for EP1 has a two-layer structure and can store up to 128  
bytes of data. This bit indicates the status of the FIFO in which data being written at  
that time. In other words, this bit indicates the status of the FIFO into which the host  
computer is writing data when EP1 is receiving data, and of the FIFO into which the  
local MCU is writing data when EP1 is transmitting data.  
FIFO1 Empty:  
This bit becomes “1” when the FIFO for EP1 is empty. This is true during both  
transmission and reception. The FIFO for EP1 has a two-layer structure and can store  
up to 128 bytes of data. This bit indicates the status of the FIFO which is being read  
out at that time.  
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