PEDL60851C-02
1
Semiconductor
ML60851C
FIFO0 Status Register 2 (FIFOSTAT2)
Read address
Write address
C4h
—
D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
0
After a hardware reset
After a bus reset
Definition
0
0
1
0
1
0
1
0
0
0
Transmit FIFO0 Full (R)
Transmit FIFO0 Empty (R)
FIFO2 Full (R)
FIFO2 Empty (R)
FIFO3 Full (R)
FIFO3 Empty (R)
This register reports the statuses of the EP0TXFIFO, the FIFO for EP2, and the FIFO for EP3. Normally, there is
no need to read this register because it is sufficient to read the packet ready status before reading out or writing in
a FIFO.
Transmit FIFO0 Full: This bit becomes “1” when 8-bytes of data is stored in the EP0TXFIFO. This bit is
not set to “1” when a packet less than 8 bytes (a short packet) is written in.
Transmit FIFO0 Empty: This bit will be “1” when the EP0 transmit FIFO0 is empty.
FIFO2 Full:
This bit becomes “1” when 64 bytes of data is either stored or written in the FIFO for
EP2. This bit does not become “1” in the case of a short packet.
This bit becomes “1” when the FIFO of EP2 is empty.
This bit becomes “1” when 64 bytes are written in the FIFO for EP3. This bit does not
become “1” in the case of a short packet.
FIFO2 Empty:
FIFO3 Full:
FIFO3 Empty:
This bit becomes “1” when the FIFO for EP3 is empty.
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