PEDL60851C-02
1
Semiconductor
ML60851C
End Point 2 Receive Byte Count Register (EP2RXCNT)
Read address
Write address
CBh
—
D7
0
D6
0
D5
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
0
0
0
Byte Count of EP2 (R)
The ML60851C automatically counts the number of bytes in the packet being received by EP2 and stored it in this
register. Although the counting is performed up to the maximum packet size entered in the payload register in the
case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to
this value and reads the data of one packet from the EP2RXFIFO.
This register is invalid when the EP2 transfer direction is set as ‘Transmit’.
The EP2 receive byte count register is cleared under the following conditions:
1. When an OUT token is received for EP2.
2. When the EP2 receive packet ready bit is reset (by writing a “1” in PKTRDY(2)).
3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).
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