Philips Semiconductors
Product specification
Economy Autosync Deflection Controller
(EASDC)
TDA4858
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VERTICAL SYNC OUTPUT AT VSYNC (PIN 14) DURING COMPOSITE SYNC AT HSYNC (PIN 15)
IVSYNC
output current
during internal vertical
sync
−0.7
4.4
−
−1.0
−1.35
5.2
−
mA
VVSYNC
internal clamping voltage level during internal vertical
sync
4.8
V
steepness of slopes
300
ns/mA
Automatic polarity correction for vertical sync
tVSYNC(max)
maximum width of vertical sync
pulse
−
−
−
300
1.8
µs
td(VPOL)
delay for changing polarity
0.3
ms
Video clamping/vertical blanking output [CLBL (pin 16)]
tclamp(CLBL)
Vclamp(CLBL)
width of video clamping pulse
measured at VCLBL = 3 V 0.6
0.7
0.8
µs
top voltage level of video
clamping pulse
4.32
4.75
5.23
V
TCclamp
temperature coefficient of
Vclamp(CLBL)
−
+4
50
1.9
−
mV/K
ns/V
V
steepness of slopes for
clamping pulse
RL = 1 MΩ; CL = 20 pF
−
−
Vblank(CLBL)
top voltage level of vertical
blanking pulse
note 1
1.7
2.1
tblank(CLBL)
TCblank
width of vertical blanking pulse
240
300
+2
360
µs
temperature coefficient of
Vblank(CLBL)
−
−
mV/K
Vscan(CLBL)
TCscan
output voltage during vertical
scan
ICLBL = 0
0.59
0.63
0.67
V
temperature coefficient of
Vscan(CLBL)
−
−2
−
mV/K
Isink(CLBL)
Iload(CLBL)
internal sink current
external load current
2.4
−
−
−
mA
mA
−
−3.0
SELECTION OF LEADING/TRAILING EDGE TRIGGER FOR VIDEO CLAMPING PULSE
VCLSEL
voltage at CLSEL (pin 10) for
trigger with leading edge of
horizontal sync
7
0
−
−
−
VCC
V
voltage at CLSEL for trigger
with trailing edge of horizontal
sync
−
5
V
td(clamp)
delay between leading edge of VCLSEL > 7 V
horizontal sync and start of
horizontal clamping pulse
300
130
−
ns
ns
delay between trailing edge of
horizontal sync and start of
horizontal clamping pulse
VCLSEL < 5 V
−
1997 Oct 27
14
NXP [ NXP ]
