NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
VIN
SW1AIN
SW1AMODE
I
SENSE
C
INSW1A
CONTROLLER
SW1AB
SW1ALX
DRIVER
L
SW1A
SW1AFAULT
C
OSW1A
INTERNAL
COMPENSATION
I2C
Z2
SW1FB
Z1
EA
V
REF
DAC
VIN
SW1BIN
SW1BMODE
I
SENSE
C
INSW1B
2
I C
CONTROLLER
INTERFACE
SW1BLX
DRIVER
L
SW1B
SW1BFAULT
SW1CMODE
C
OSW1B
VIN
SW1CIN
I
SENSE
C
INSW1C
CONTROLLER
SW1C
SW1CLX
EP
DRIVER
L
SW1C
SW1CFAULT
C
OSW1C
INTERNAL
COMPENSATION
I2C
Z2
SW1CFB
Z1
EA
V
REF
DAC
aaa-026481
Figure 12.ꢀSW1A/B dual phase, SW1C independent mode block diagram
In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at
180 ° phase shift from each other and use the same frequency and DVS configured
by SW1ABCONF register, while SW1CLX node operate independently using the
configuration in the SW1CCONF register.
10.4.4.3.4 SW1A/B/C setup and control registers
SW1A/B and SW1C output voltages are programmable from 0.300 V to 1.875 V in steps
of 25 mV. The output voltage set point is independently programmed for normal, standby,
and sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits
respectively. Table 39 shows the output voltage coding for SW1A/B or SW1C.
Note: Voltage set points of 0.6 V and below are not supported.
Table 39.ꢀSW1A/B/C output voltage configuration
Set point
SW1x[5:0]
SW1x output (V)
Set point
SW1x[5:0]
SW1x output (V)
SW1xSTBY[5:0]
SW1xOFF[5:0]
SW1xSTBY[5:0]
SW1xOFF[5:0]
0
000000
0.3000
32
100000
1.1000
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
41 / 137
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