NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Table 123.ꢀRegister INTSENSE3 - ADDR 0x10
Name
Bit number
R/W
Default Description
SWBSTFAULTS
0
R
0
SWBST overcurrent limit sense bit
• 0 = Normal operation
• 1 = Above current limit
UNUSED
6:1
7
—
R
0x00
0
unused
OTP_ECCS
OTP error sense bit
• 0 = No error detected
• 1 = OTP error detected
Table 124.ꢀRegister INTSTAT4 - ADDR 0x11
Name
Bit number
R/W
Default Description
VGEN1FAULTI
VGEN2FAULTI
VGEN3FAULTI
VGEN4FAULTI
VGEN5FAULTI
VGEN6FAULTI
UNUSED
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
—
0
VGEN1 overcurrent interrupt bit
1
0
VGEN2 overcurrent interrupt bit
VGEN3 overcurrent interrupt bit
VGEN4 overcurrent interrupt bit
VGEN5 overcurrent interrupt bit
VGEN6 overcurrent interrupt bit
unused
2
0
3
0
4
0
5
0
7:6
00
Table 125.ꢀRegister INTMASK4 - ADDR 0x12
Name
Bit number
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Default Description
VGEN1FAULTM
VGEN2FAULTM
VGEN3FAULTM
VGEN4FAULTM
VGEN5FAULTM
VGEN6FAULTM
UNUSED
0
1
VGEN1 overcurrent interrupt mask bit
1
1
VGEN2 overcurrent interrupt mask bit
VGEN3 overcurrent interrupt mask bit
VGEN4 overcurrent interrupt mask bit
VGEN5 overcurrent interrupt mask bit
VGEN6 overcurrent interrupt mask bit
unused
2
1
3
1
4
1
5
1
7:6
00
Table 126.ꢀRegister INTSENSE4 - ADDR 0x13
Name
Bit number
R/W
Default Description
VGEN1FAULTS
0
R
0
VGEN1 overcurrent sense bit
• 0 = Normal operation
• 1 = Above current limit
VGEN2FAULTS
1
R
0
VGEN2 overcurrent sense bit
• 0 = Normal operation
• 1 = Above current limit
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
111 / 137
NXP [ NXP ]
