NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Interrupt
Mask
Sense
Purpose
Trigger Debounce
time (ms)
OTP_ECCI
OTP_ECCM
OTP_ECCS
1 or 2 bit error detected in OTP
registers
L to H
8.0
Sense is 1 if error detected
[1] Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
A full description of all interrupt, mask, and sense registers is provided in Table 115 to
Table 126.
Table 115.ꢀRegister INTSTAT0 - ADDR 0x05
Name
Bit number
R/W
Default Description
PWRONI
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
—
0
Power on interrupt bit
LOWVINI
1
0
Low-voltage interrupt bit
110 °C Thermal interrupt bit
120 °C Thermal interrupt bit
125 °C Thermal interrupt bit
130 °C Thermal interrupt bit
unused
THERM110I
THERM120I
THERM125I
THERM130I
UNUSED
2
0
3
0
4
0
5
0
7:6
00
Table 116.ꢀRegister INTMASK0 - ADDR 0x06
Name
Bit number
R/W
Default Description
PWRONM
LOWVINM
THERM110M
THERM120M
THERM125M
THERM130M
UNUSED
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
—
1
Power on interrupt mask bit
1
1
Low-voltage interrupt mask bit
110 °C thermal interrupt mask bit
120 °C thermal interrupt mask bit
125 °C thermal interrupt mask bit
130 °C thermal interrupt mask bit
unused
2
1
3
1
4
1
5
1
7:6
00
Table 117.ꢀRegister INTSENSE0 - ADDR 0x07
Name
Bit number
R/W
Default Description
PWRONS
0
R
0
0
0
Power on sense bit
• 0 = PWRON low
• 1 = PWRON high
LOWVINS
1
2
R
R
Low-voltage sense bit
• 0 = VIN > 2.8 V
• 1 = VIN ≤ 2.8 V
THERM110S
110 °C thermal sense bit
• 0 = Below threshold
• 1 = Above threshold
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
108 / 137
NXP [ NXP ]
