NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
The following examples show how to write and read data to and from the IC. The host
initiates and terminates all communication. The host sends a master command packet
after driving the start condition. The device responds to the host if the master command
packet contains the corresponding slave address. In the following examples, the device
is shown always responding with an ACK to transmissions from the host. If at any time
a NACK is received, the host should terminate the current transaction and retry the
transaction.
2
I C write example
host can also drive
another START
instead of STOP
device address
register address
master driven data
DATA (byte 0)
SDA
S
0
A
A
A
P
acknowledge
from slave
acknowledge STOP
from slave condition
START condition
R/W
acknowledge
from slave
2
host can also drive
another START
instead of STOP
I C read example
device address
register address
device address
PMIC driven data
SDA
S
0
A
A
S
1
A
NA P
acknowledge
from slave
no acknowledge STOP
from slave condition
START condition
START condition
R/W
R/W
acknowledge
from slave
acknowledge
from slave
aaa-026501
Figure 32.ꢀI2C sequence
10.5.3 Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt
events are signaled to the processor by driving the INTB pin low.
Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt
remains set until cleared. Each interrupt can be cleared by writing a 1 to the appropriate
bit in the Interrupt Status register; this also causes the INTB pin to go high. If there are
multiple interrupt bits set, the INTB pin remains low until all are either masked or cleared.
If a new interrupt occurs while the processor clears an existing interrupt bit, the INTB pin
remains low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a
result, when a masked interrupt bit goes high, the INTB pin does not go low. A masked
interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked,
so the processor must initially poll the device to determine if any interrupts are active.
Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt
bit was already high, the INTB pin goes low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll
the current state of interrupt sources. They are read only, and not latched or clearable.
Interrupts generated by external events are debounced; therefore, the event needs to
be stable throughout the debounce period before an interrupt is generated. Nominal
debounce periods for each event are documented in the INT summary Table 114. Due
to the asynchronous nature of the debounce timer, the effective debounce time can vary
slightly.
10.5.4 Interrupt bit summary
Table 114 summarizes all interrupt, mask, and sense bits associated with INTB control.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
106 / 137
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