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LPC54616J512BD100 参数 Datasheet PDF下载

LPC54616J512BD100图片预览
型号: LPC54616J512BD100
PDF下载: 下载PDF文件 查看货源
内容描述: [32-bit ARM Cortex-M4 microcontroller]
分类和应用:
文件页数/大小: 169 页 / 3528 K
品牌: NXP [ NXP ]
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LPC546xx  
NXP Semiconductors  
32-bit ARM Cortex-M4 microcontroller  
Table 5.  
Pin  
Termination of unused pins  
Default Recommended termination of unused pins  
state[1]  
USBn_DM  
F
Can be left unconnected. If USB interface is not used, pin can be left unconnected  
except in deep power-down mode where it must be externally pulled low. When the  
USB PHY is disabled, the pins are floating.  
USB1_AVSCC  
USB1_VBUS  
F
F
F
F
F
F
Tie to VSS.  
Tie to VDD.  
USB1_AVDDC3V3  
USB1_AVDDTX3V3  
USB1_AVSSTX3V3  
USB1_ID  
Tie to VDD.  
Tie to VDD.  
Tie to VSS.  
Can be left unconnected. If USB interface is not used, pin can be left unconnected.  
[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating  
6.2.2 Pin states in different power modes  
Table 6.  
Pin  
Pin states in different power modes  
Active  
Sleep  
Deep-sleep  
Deep  
power-down[2]  
PIOn_m pins (not I2C)  
PIO0_13 to PIO0_14 (open-drain As configured in the IOCON[1].  
I2C-bus pins)  
As configured in the IOCON[1]. Default: internal pull-up enabled.  
Floating  
Floating  
PIO3_23 to PIO3_24 (open-drain As configured in the IOCON[1].  
I2C-bus pins)  
Floating  
RESET  
Reset function enabled. Default: input, internal pull-up enabled.  
Reset function disabled.  
[1] Default and programmed pin states are retained in sleep and deep-sleep.  
[2] If VBAT> VDD, the external reset pin must be floating to prevent high VBAT leakage.  
LPC546xx  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2018. All rights reserved.  
Product data sheet  
Rev. 2.5 — 20 June 2018  
54 of 169  
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