LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
18. Revision history
Table 60. Revision history
Document ID
Release date Data sheet status
20180620 Product data sheet
Change notice Supersedes
LPC546xx v.2.5
Modifications:
LPC546xx v.2.4
• Updated Figure 14 “Typical CoreMark score (iterations/s/MHz) vs. Frequency (MHz)
from flash and SRAMX”
• Updated Table 14 “CoreMark score[1]”.
• Updated Table 4 “Pin description”: Description of VREFN and VSSA.
• Updated Table 5 “Termination of unused pins”: Added USB1_ID pin.
LPC546xx v.2.4
Modifications:
20180524
Product data sheet
201805030I
LPC546xx v.2.3
• Added text to serial interfaces to Section 2 “Features and benefits”: USB 2.0 full-speed
host/device controller with on-chip PHY and dedicated DMA controller supporting
crystal-less operation in device mode using software library. See Technical note
TN00032 for more details.
• Added table note 2 of Section 6.2.2 “Pin states in different power modes”: If VBAT>
VDD, the external reset pin must be floating to prevent high VBAT leakage.
• Added table note 3 to Table 18 “Static characteristics: Power consumption in deep
power-down mode”: If VBAT> VDD, the external reset pin must be floating to prevent
high VBAT leakage.
• Added remark to Figure 16 “Deep-sleep mode: Typical supply current IDD versus
temperature for different supply voltages VDD”: At hot temperature and below 2.0 V,
the supply current could increase slightly because of reduction of available RBB
(reverse body bias) voltage.
• Updated Table 16 “Static characteristics: Power consumption in deep-sleep and deep
power-down modes”: IDD supply current, Deep-sleep mode; Flash is powered down for
SRAMX (32 KB) powered Tamb = 25 C and Tamb = 105 C; Max values: 69 A and
1150 A. Updated table note 3: Tested in production. VDD = 1.71 V. At hot temperature
and below 2.0 V, the supply current could increase slightly because of reduction of
available RBB (reverse body bias) voltage.
• Updated Table 17 “Static characteristics: Power consumption in deep-sleep and deep
power-down modes”: IDD supply current, Deep-sleep mode; Flash is powered down for
SRAMX (32 KB) powered Tamb = 25 C; Max value: 69 A.
LPC546xx v.2.3
Modifications:
LPC546xx v.2.2
Modifications:
20180426
• Updated Table 4 “Pin description”: VREFN and VSSA.
20180417 Product data sheet
Product data sheet
-
LPC546xx v.2.2
-
LPC546xx v.2.1
• Updated Table 25 “Dynamic characteristic: Typical wake-up times from low power
modes”: Changed twake at typical for deep-sleep mode to 150 s. Was 19 s.
LPC546xx v.2.1
Modifications:
20180206
Product data sheet
-
LPC546xx v.2.0
• Updated Figure 3 “LQFP100 package marking”.
• Fixed Figure 4 “LPC546xx Block diagram” figure number identifier.
• Fixed Figure 9 “LPC546xx Memory mapping” figure number identifier.
LPC546xx v.2.0
20180126
Product data sheet
-
LPC546xx v.1.9
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
162 of 169
NXP [ NXP ]
