LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 60. Revision history …continued
Document ID
Release date Data sheet status
Change notice Supersedes
Modifications:
• Updated a feature in Section 7.17.8.2 “SPI serial I/O controller”: Maximum data rate of
48 Mbit/s in master mode and 14 Mbit/s in slave mode for SPI functions. Was 71 Mbit/s
in master mode.
• Updated Section 11.15 “SPI interfaces”: the maximum supported bit rate for SPI
master mode is 48 Mbit/s. Was 71 Mbit/s.
• Updated Table 4 “Pin description”: Changed restate state of PIO3_23 and PIO0_24 to
Z. Added footnote True open-drain pin. I2C-bus pins compliant with the I2C-bus
specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin
requires an external pull-up to provide output functionality. When power is switched off,
this pin is floating and does not disturb the I2C lines. Open-drain configuration applies
to all functions on this pin to PIO3_23 and PIO0_24.
LPC546xx v.1.9
Modifications:
20171109
Product data sheet
-
LPC546xx v.1.8
• Updated Table 1 “Ordering information” and Table 2 “Ordering options”. Added the part
numbers: LPC54605J256BD100, LPC54605J512BD100, LPC54605J256ET100,
LPC54605J512ET100.
LPC546xx v.1.8
Modifications:
20170614
Product data sheet
-
LPC546xx v.1.7
• Updated Section 13.7 “Suggested USB interface solutions”. Removed the remark.
• Added LPC5462x device to the data sheet.
• Updated Timer and digital peripherals of Section 2 “Features and benefits”.
• Updated Section 7.19.2 “SCTimer/PWM”, Section 7.19.2.1 “Features” and Section
7.18.3 “External memory controller”.
• Updated Figure 13 “Typical CoreMark score (iterations/s) vs. Frequency (MHz) from
flash and SRAMX” and Figure 14 “CoreMark power consumption: typical mA/MHz vs.
frequency (MHz) from flash and SRAMX”.
• Updated Table 42 “Dynamic characteristics: I2S-bus interface pins [1][4]”, Table 43
“SPI dynamic characteristics[1]”, Table 44 “Dynamic characteristics: SPIFI[1]”, Table
45 “Dynamic characteristics[1]”, Table 46 “Dynamic characteristics[1]”, Table 47
“USART dynamic characteristics[1]”, Table 50 “Dynamic characteristics: Ethernet”,
Table 51 “Dynamic characteristics: SD/MMC and SDIO”, and Table 52 “Dynamic
characteristics: LCD”: replaced the condition, CCLK > 100 MHz with 100 MHz <CCLK
≤ 180 MHz
• Updated Table 12 “General operating conditions”. Added the condition, For OTP
programming only to fclk
.
• Added Remark to Section 7.24 “Code security (enhanced Code Read Protection -
eCRP)”.
• Updated Table 19 “Typical peripheral power consumption[1][2]”: added SYSOSC
value.
• Updated Table 14 “CoreMark score[1]”.
• Updated Table 15 “Static characteristics: Power consumption in active and sleep
mode”: IDD supply current in Active mode: CoreMark code executed from flash.
• Updated Figure 13 “Typical CoreMark score (iterations/s) vs. Frequency (MHz) from
flash and SRAMX” and Figure 14 “CoreMark power consumption: typical mA/MHz vs.
frequency (MHz) from flash and SRAMX”.
LPC546xx v.1.7
Modifications:
20170428
Product data sheet
-
LPC546xx v.1.6
• Updated Table 42 “Dynamic characteristics: I2S-bus interface pins [1][4]”.
• Updated Table 11 “Thermal resistance”.
LPC546xx v.1.6
Modifications:
Product data sheet
-
LPC546xx v.1.5
• Added TFBGA100 and LQFP100 packages.
LPC546xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
163 of 169
NXP [ NXP ]
