LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 7.
Memory usage and details …continued
Address range
General Use
Address range details and description
0x8000 0000 to 0xDFFF FFFF Off-chip Memory Four static memory chip selects:
via the External
0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64
Memory
Controller
MB)[1]
0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64
MB)[2]
0x9000 0000 – 0x93FF FFFF Static memory chip select 2 (up to 64
MB).
0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64
MB).
Four dynamic memory chip selects:
0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to
256 MB).
0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to
256 MB).
0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to
256 MB).
0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to
256 MB).
0xE000 0000 to 0xE00F FFFF Cortex-M4
Private
0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes
the NVIC and System Tick Timer.
Peripheral Bus
[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See the
EMCSYSCTRL register bit 0 in the LPC540xx user manual.
[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See the
EMCSYSCTRL register bit 0 in the LPC540xx user manual.
Figure 9 shows the overall map of the entire address space from the user program
viewpoint following reset.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
59 of 168
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