LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• Supports up to 54 vectored interrupts.
• Eight programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.6 System Tick timer (SysTick)
The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a
dedicated SYSTICK exception. The clock source for the SysTick can be the FRO or the
Cortex-M4 core clock.
7.7 On-chip static RAM
The LPC540xx support 360 kB SRAM with separate bus master access for higher
throughput and individual power control for low-power operation.
7.8 On-chip ROM
The 64 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-Application Programming (IAP) and In-System Programming (ISP).
• ROM-based USB drivers (HID, CDC, MSC, and DFU).
• Supports serial interface booting (UART, I2C, SPI) from an application processor,
automated booting from NOR flash (quad SPIFI, 8/16/32-bit external parallel flash),
and USB booting (full-speed, high speed).
• Execute in place (XIP) from SPIFI NOR flash (in quad, dual SPIFI mode or single-bit
SPI mode), and parallel NOR flash.
• FRO API for selecting FRO output frequency.
• OTP API for programming OTP memory.
• Random Number Generator (RNG) API.
LPC540xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
57 of 168
NXP [ NXP ]
