LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 5.
Pin
Termination of unused pins
Default
Recommended termination of unused pins
state[1][2]
VBAT
-
Tie to VDD.
USBn_DP
F
Can be left unconnected. If USB interface is not used, pin can be left unconnected
except in deep power-down mode where it must be externally pulled low. When the
USB PHY is disabled, the pins are floating.
USBn_DM
F
Can be left unconnected. If USB interface is not used, pin can be left unconnected
except in deep power-down mode where it must be externally pulled low. When the
USB PHY is disabled, the pins are floating.
USB1_AVSCC
USB1_VBUS
F
F
F
F
F
F
Tie to VSS.
Tie to VDD.
USB1_AVDDC3V3
USB1_AVDDTX3V3
USB1_AVSSTX3V3
USB1_ID
Tie to VDD.
Tie to VDD.
Tie to VSS.
Can be left unconnected. If USB interface is not used, pin can be left unconnected.
[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating
[2] For initial device revision 0A (Boot ROM version 21.0), PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). For
future device revision 1B (Boot ROM version 21.1), Z = high impedance; pull-up or pull-down disabled. See the Errata sheet LPC540xx
(IOCON.1) for more details. For future device revision 1B (Boot ROM version 21.1), GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3,
PIO0_4, PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by
default. If unused, it is recommended to externally terminate this pins to prevent leakage.
6.2.2 Pin states in different power modes
Table 6.
Pin
Pin states in different power modes
Active
Sleep
Deep-sleep
Deep
power-down[3]
PIOn_m pins (not I2C)
As configured in the IOCON[1]. Default: internal pull-up enabled Floating
or high Z [2]
.
PIO0_13 to PIO0_14 (open-drain As configured in the IOCON[1].
I2C-bus pins)
Floating
PIO3_23 to PIO3_24 (open-drain As configured in the IOCON[1].
I2C-bus pins)
Floating
RESET
Reset function enabled. Default: input, internal pull-up enabled.
Reset function disabled.
[1] Default and programmed pin states are retained in sleep and deep-sleep.
[2] For initial device revision 0A (Boot ROM version 21.0), PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). For
future device revision 1B (Boot ROM version 21.1), Z = high impedance; pull-up or pull-down disabled. See the Errata sheet LPC540xx
(IOCON.1) for more details. For future device revision 1B (Boot ROM version 21.1), GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3,
PIO0_4, PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by
default. If unused, it is recommended to externally terminate this pins to prevent leakage.
[3] If VBAT> VDD, the external reset pin must be floating to prevent high VBAT leakage.
LPC540xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
55 of 168
NXP [ NXP ]
