LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.11 I2C-bus
Table 38. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V.[2]
Symbol Parameter
Conditions
Min
Max
100
400
1
Unit
kHz
kHz
MHz
ns
fSCL
SCL clock frequency
fall time
Standard-mode
Fast-mode
0
0
0
-
Fast-mode Plus
Both SDA and SCL signals
Standard-mode
Fast-mode
[4][5][6][7]
tf
300
20 + 0.1
300
ns
Cb
Fast-mode Plus
Standard-mode
Fast-mode
-
120
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
data hold time
4.7
1.3
0.5
4.0
0.6
0.26
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
tHIGH
Fast-mode Plus
Standard-mode
Fast-mode
[3][4][8]
[9][10]
tHD;DAT
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up time
250
100
50
Fast-mode Plus
[1] Guaranteed by design. Not tested in production.
[2] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
t
VD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
118 of 168
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