LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 39. Dynamic characteristics: I2S-bus interface pins [1][4]
Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter
Conditions
Min
Typ[3] Max
Unit
Master; 2.7 V VDD 3.6 V
[2]
tv(Q)
data output valid time on pin I2Sx_TX_SDA
CCLK 100 MHz
21.4
20.6
-
-
30.4
28.7
ns
ns
CCLK > 100 MHz
on pin I2Sx_WS
CCLK 100 MHz
21.1
20.3
-
-
29
ns
ns
CCLK > 100 MHz
28.3
[2]
[2]
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
CCLK 100 MHz
1.3
1.0
-
-
-
-
ns
ns
CCLK > 100 MHz
th(D)
data input hold time
on pin I2Sx_RX_SDA
CCLK 100 MHz
CCLK > 100 MHz
2.9
3.3
-
-
-
-
ns
ns
Slave; 2.7 V VDD 3.6 V
[2]
[2]
tv(Q)
data output valid time on pin I2Sx_TX_SDA
CCLK 100 MHz
13.8
13
-
-
23.6
21.9
ns
ns
CCLK > 100 MHz
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
CCLK 100 MHz
4.7
4.2
-
-
-
-
ns
ns
CCLK > 100 MHz
on pin I2Sx_WS
CCLK 100 MHz
0.9
0.7
-
-
-
-
ns
ns
CCLK > 100 MHz
[2]
th(D)
data input hold time
on pin I2Sx_RX_SDA
CCLK 100 MHz
CCLK > 100 MHz
on pin I2Sx_WS
0
0
-
-
-
-
ns
ns
CCLK 100 MHz
CCLK > 100 MHz
1.5
1.3
-
-
-
-
ns
ns
[1] Based on characterization; not tested in production.
[2] Clock Divider register (DIV) = 0x0.
[3] Typical ratings are not guaranteed.
[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section
in the I2S chapter (UM11060) to calculate clock and sample rates.
[5] Based on simulation. Not tested in production.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
121 of 168
NXP [ NXP ]
