LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.12 I2S-bus interface
Table 39. Dynamic characteristics: I2S-bus interface pins [1][4]
Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter
Conditions
Min
Typ[3] Max
Unit
Common to master and slave
tWH
pulse width HIGH
pulse width LOW
on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]
CCLK 100 MHz
(Tcyc/2)-1 -
(Tcyc/2)-1 -
(Tcyc/2) +1 ns
CCLK > 100 MHz
(Tcyc/2) +1 ns
tWL
on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]
CCLK 100 MHz
(Tcyc/2)-1 -
(Tcyc/2)-1 -
(Tcyc/2) +1 ns
(Tcyc/2) +1 ns
CCLK > 100 MHz
Master; 1.71 V VDD 2.7 V
[2]
tv(Q)
data output valid time on pin I2Sx_TX_SDA
CCLK 100 MHz
26.0
25.0
-
-
40.3
39.0
ns
ns
CCLK > 100 MHz
on pin I2Sx_WS
CCLK 100 MHz
26.0
25.0
-
-
41.0
39.6
ns
ns
CCLK > 100 MHz
[2]
[2]
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
CCLK 100 MHz
0
0
-
-
-
-
ns
ns
CCLK > 100 MHz
th(D)
data input hold time
on pin I2Sx_RX_SDA
CCLK 100 MHz
CCLK > 100 MHz
6.1
6.4
-
-
-
-
ns
ns
Slave; 1.71 V VDD 2.7 V
[2]
[2]
tv(Q)
data output valid time on pin I2Sx_TX_SDA
CCLK 100 MHz
18.8
18.0
-
-
37.1
35.5
ns
ns
CCLK > 100 MHz
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
CCLK 100 MHz
4.8
4.4
-
-
-
-
ns
ns
CCLK > 100 MHz
on pin I2Sx_WS
CCLK 100 MHz
0
0
-
-
-
-
ns
ns
CCLK > 100 MHz
[2]
th(D)
data input hold time
on pin I2Sx_RX_SDA
CCLK 100 MHz
CCLK > 100 MHz
on pin I2Sx_WS
0
0
-
-
-
-
ns
ns
CCLK 100 MHz
CCLK > 100 MHz
3.2
3.2
-
-
-
-
ns
ns
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
120 of 168
NXP [ NXP ]
