LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 33. Dynamic characteristics of the PLL2[1]
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Reference clock input
Fin
input frequency
1
-
25
MHz
Clock output
[2]
fo
output frequency
for PLL2 clkout
output
4.3
46
-
-
-
550
54
MHz
%
do
output duty cycle
CCO frequency
for PLL2 clkout
output
fCCO
275
550
MHz
Lock detector output
lock(PFD) PFD lock criterion
[3]
1
2
4
ns
Dynamic parameters at fout = fCCO = 540 MHz; standard bandwidth settings
[4][5]
Jrms-interval RMS interval jitter
fref = 10 MHz
-
-
15 30
40 80
ps
ps
[4][5]
Jpp-period
peak-to-peak, period fref = 10 MHz
jitter
[1] Data based on characterization results, not tested in production.
[2] Excluding under- and overshoot which may occur when the PLL is not in lock.
[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion
means lock output is HIGH.
[4] Actual jitter dependent on amplitude and spectrum of substrate noise.
[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.
11.7 FRO
The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.
Table 34. Dynamic characteristic: FRO
Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V.
Symbol
fosc(RC)
fosc(RC)
fosc(RC)
Parameter
Conditions Min
Typ[1]
12
Max
Unit
MHz
MHz
MHz
FRO clock frequency
FRO clock frequency
FRO clock frequency
-
-
-
11.88
12.12
48.48
96.96
47.52
95.04
48
96
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.8 Crystal oscillator
Table 35. Dynamic characteristic: oscillator
Tamb = 40 C to +105 C; 1.71 V VDD 3.6 V.[1]
Symbol
Low-frequency mode (1-20 MHz)[4]
tjit(per) period jitter time
Parameter
Conditions
Min
Typ[2]
Max
Unit
[3]
5 MHz crystal
10 MHz crystal
15 MHz crystal
-
-
-
13.2
6.6
-
-
-
ps
ps
ps
4.8
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
115 of 168
NXP [ NXP ]
