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LPC54018JBD208 参数 Datasheet PDF下载

LPC54018JBD208图片预览
型号: LPC54018JBD208
PDF下载: 下载PDF文件 查看货源
内容描述: [32-bit ARM Cortex-M4 microcontroller]
分类和应用:
文件页数/大小: 168 页 / 3551 K
品牌: NXP [ NXP ]
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LPC540xx  
NXP Semiconductors  
32-bit ARM Cortex-M4 microcontroller  
11.5 USB PLL (PLL1)  
Table 30. PLL1 lock times and current  
amb = 40 C to +105 C, unless otherwise specified. VDD = 1.71 V to 3.6 V  
T
Symbol Parameter Conditions  
PLL1 configuration: input frequency 12 MHz; output frequency 48 MHz  
Min  
Typ Max  
Unit  
[1]  
tlock(PLL1)  
IDD(PLL1)  
PLL1 lock time  
PLL1 current  
-
-
7.4  
-
-
s  
[1][2]  
When locked  
260  
A  
[1] Data based on characterization results, not tested in production.  
[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.  
Table 31. Dynamic characteristics of the PLL1[1]  
Symbol  
Parameter  
Conditions  
Min  
Typ Max  
Unit  
Reference clock input  
Fin  
input frequency  
1
-
25  
MHz  
Clock output  
[2]  
fo  
output frequency  
for PLL1 clkout  
output  
9.75  
45  
-
-
-
160  
55  
MHz  
%
do  
output duty cycle  
CCO frequency  
for PLL1 clkout  
output  
fCCO  
156  
320  
MHz  
Dynamic parameters at fout = fCCO = 320 MHz; standard bandwidth settings  
[3][4]  
Jpp-period  
peak-to-peak, period fref = 4 MHz  
jitter  
-
-
300  
ps  
[1] Data based on simulation, not tested in production.  
[2] Excluding under- and overshoot which may occur when the PLL is not in lock.  
[3] Actual jitter dependent on amplitude and spectrum of substrate noise.  
[4] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.  
11.6 Audio PLL (PLL2)  
Table 32. PLL2 lock times and current  
Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.71 V to 3.6 V  
Symbol  
Parameter  
Conditions  
Min Typ Max  
Unit  
PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz  
[1]  
tlock(PLL2)  
IDD(PLL2)  
PLL2 lock time  
PLL2 current  
-
-
-
-
96  
s  
[1][2]  
when locked  
2.0  
mA  
PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz  
[1]  
tlock(PLL2)  
IDD(PLL2)  
PLL2 lock time  
PLL2 current  
-
-
-
-
108  
1.6  
s  
[1][2]  
when locked  
mA  
[1] Data based on characterization results, not tested in production.  
[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.  
LPC540xx  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2018. All rights reserved.  
Product data sheet  
Rev. 1.8 — 22 June 2018  
114 of 168  
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