LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 26. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2]
CL = 20 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB. Values based on simulation. tcmddly is programmable delay value for EMC
command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input
data sampling.
Symbol
Parameter
Min
Typ
Max
Unit
For RD = 1
Common to read and write cycles
[1]
Tcy(clk)
td(SV)
clock cycle time
10
-
-
-
-
-
ns
ns
ns
ns
chip select valid delay time
chip select hold time
-
tcmddly + 4.9
-
th(S)
tcmddly + 2.4
-
td(RASV)
row address strobe valid
delay time
tcmddly + 5.4
th(RAS)
td(CASV)
th(CAS)
row address strobe hold
time
tcmddly + 2.5
-
-
-
-
-
ns
ns
ns
column address strobe valid
delay time
tcmddly + 5.6
-
column address strobe hold
time
tcmddly + 2.6
td(WV)
th(W)
td(AV)
th(A)
write valid delay time
write hold time
-
-
-
-
-
tcmddly + 6.3
ns
ns
ns
ns
tcmddly + 3.1
-
-
address valid delay time
address hold time
tcmddly + 6.1
-
tcmddly + 2.4
Read cycle parameters
tsu(D) data input set-up time
th(D) data input hold time
Write cycle parameters
td(QV) data output valid delay time
th(Q) data output hold time
0.5
2.1
-
-
-
-
ns
ns
-
-
-
9.3
-
ns
ns
2.4
[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.
[2] See Table 27 for internal programmable delay.
LPC540xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
110 of 168
NXP [ NXP ]
