LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 27. Dynamic characteristics: Dynamic external memory interface programmable clock delays (CMDDLY,
FBCLKDLY)
Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V.Values guaranteed by design. tcmddly is programmable delay value for EMC
command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input
data sampling.
Symbols
Parameter Five bit value for each delay in EMCDLYCTL[1] Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcmddly, tfbdly
delay time
b00000
b00001
b00010
b00011
b00100
b00101
b00110
b00111
b01000
b01001
b01010
b01011
b01100
b01101
b01110
b01111
b10000
b10001
b10010
b10011
b10100
b10101
b10110
b10111
b11000
b11001
b11010
b11011
b11100
b11101
b11110
b11111
0.41
0.52
0.69
0.8
0.66 0.77
0.85 1.03
1.11 1.3
1.3
1.56
0.95
1.06
1.23
1.34
1.45
1.56
1.73
1.84
1.99
2.1
1.53 1.77
1.72 2.03
1.98 2.3
2.17 2.56
2.3
2.67
2.49 2.93
2.75 3.2
2.94 3.46
3.17 3.67
3.36 3.93
3.62 4.2
3.81 4.46
3.86 4.46
4.05 4.72
4.31 4.99
2.27
2.38
2.45
2.56
2.73
2.84
2.99
3.1
4.5
5.25
4.73 5.46
4.92 5.72
5.18 5.99
5.37 6.25
3.27
3.38
3.49
3.6
5.5
6.36
5.69 6.62
5.95 6.89
6.14 7.15
6.37 7.36
6.56 7.62
6.82 7.89
7.01 8.15
3.77
3.88
4.03
4.14
4.31
4.42
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
112 of 168
NXP [ NXP ]
