LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
6.19.1 Features
• Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit timer/counter with a programmable 32-bit prescaler.
6.20 System control
6.20.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 25 MHz and up to 25 MHz with
the external oscillator. The oscillator output frequency is called fosc and the ARM
processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc
and CCLK are the same value unless the PLL is running and connected. Refer to Section
6.20.2 “PLL” for additional information.
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
28 of 50
NXP [ NXP ]
